Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) have difficulty filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating or electrodeposition, which has previously been limited to the fabrication of patterns on circuit boards, is now emerging as a preferable method for filling metal interconnects structures such as via openings (holes) and trench line openings in multi-layer semiconductor devices. Typically, electroplating (electrodeposition) uses an electrolyte including positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate (cathode) having a source of electrons to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first conformally deposited onto the semiconductor wafer to form a liner in high aspect ratio anisotropically etched features to provide a continuous electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface including etched features are electroplated with an appropriate metal, for example, aluminum or copper, to fill the features.
One exemplary process for forming a series of electrically interconnected multiple layers, for example, is a damascene or dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). In the typical multi-layer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metal-filled features such as vias and trench lines to electrically interconnect the various layers and areas within layers in the multilayer device. In most devices, pluralities of vias are separated from one another within an insulating layer included in the semiconductor wafer and selectively interconnect conductive regions between layers of a multi-layer device. Trench lines typically serve to selectively interconnect conductive regions within a layer of a multi-layer device. Vias and trench lines are selectively interconnected in order to form the necessary electrical connections to power the semiconductor device.
In filling the via openings and trench line openings with metal, for example copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer over the etched opening surfaces, such as via openings and trench line openings, depositing a metal seed layer, for example copper, over the barrier layer, and then electroplating a metal, for example copper, over the seed layer to fill the etched features to form conductive vias and trench lines. The electrodeposited copper layer, the barrier layer, and the insulating layer are then planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature within a layer of a multi-layer semiconductor device. Metal electroplating (electrodeposition) in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The electrodeposition surface is contacted with an electrical power source to form the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the electrodeposition surface, for example a semiconductor wafer surface.
More recent electroplating (electrodeposition) processes use self contained assemblies where the anode and semiconductor wafer are in close proximity to carry out both electroplating and electropolishing. Typically the semiconductor wafer surface is spaced apart from the anode in the electroplating solution during electrodeposition and contacts the anode during the electropolishing process where the electrolyte current is reversed and semiconductor wafer becomes the anode and the anode acts as a cathode. The electrolyte used in the electrodeposition and electropolishing process typically contains sulfur containing compounds such as sulfates, sulfites, and thiols and may optionally include various complexing agents including ammonia and organic compounds to aid the electrodeposition or electropolishing process. Following the electrodeposition process and electropolishing process, the semiconductor wafer surface is typically rinsed, for example, with deionized water and dried, for example, according to a wafer spinning process.
One problem with the prior art semiconductor processing methods involving rinsing and drying steps following copper electrodeposition, is that the rinsing and drying process is not fully effective in removing contaminants in the rinsing process. For example, copper features that are formed according to an electrodeposition process typically contain sulfur impurities which can react with residual moisture to form sulfuric acid thereby having a corrosive effect on semiconductor features including copper layers. It is believed that this corrosive process is at least in part responsible for subsequent semiconductor wafer defects including peeling of copper layers and lifting of copper pads deposited according to electrodeposition processes. Such peeling and lifting of copper features detrimentally affects semiconductor wafer yield and device reliability.
In addition, copper containing features in general, following exposure of an unoxidized copper containing surface, for example, following copper layer deposition, and copper CMP polishing processes, are susceptible to oxidation, forming for example, CuO, Cu2O, and CuO2, from exposure to oxygen containing atmospheres or oxidizing agents frequently included in CMP polishing compounds. In addition, the unoxidized copper surfaces are susceptible in general to contaminants present to some degree in manufacturing environmental atmospheres, for example, organics, ammonia, and sulfur containing compounds. In general, oxidation and contamination of copper containing semiconductor feature surfaces may lead to degradation of electrical performance by increasing contact resistances and facilitating electromigration thereby causing device yield and reliability concerns.
These and other shortcomings demonstrate a need in the semiconductor processing art to develop a method for reducing or preventing contamination and oxidation of copper containing semiconductor feature surfaces.
It is therefore an object of the invention to provide a method for reducing or preventing contamination and oxidation of copper containing semiconductor feature surfaces while overcoming other shortcomings and deficiencies in the prior art.